Formation of dislocations in source and drain regions of FinFET devices

ABSTRACT

Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

This application is a divisional of U.S. patent application Ser. No.14/222,401, filed on Mar. 21, 2014, entitled “Formation of Dislocationsin Source and Drain Regions of FinFET Devices,” which application ishereby incorporated herein by reference in its entirety.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application is related to U.S. application Ser. No.13/912,903, entitled “Mechanisms for Doping Lightly Doped Drain (LDD)Regions of finFET Devices” and filed on Jun. 7, 2013, and U.S.application Ser. No. 13/829,770, entitled “Epitaxial Growth of DopedFilm for Source and Drain Regions” and filed on Mar. 14, 2013. Inaddition, the present application is related to U.S. patent applicationSer. No. 13/177,309, entitled “A Semiconductor Device with a DislocationStructure and Method of Forming the Same” and filed on Jul. 6, 2011, andU.S. patent application Ser. No. 13/324,331, entitled “Mechanisms forForming Stressor Regions in a Semiconductor Device” and filed on Dec.13, 2011. Additionally, the present application is related to U.S.patent application Ser. No. 14/137,690, entitled “Mechanisms for FinFETWell Doping” and filed on Dec. 20, 2013. The above-mentionedapplications are incorporate herein in their entireties.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Over the course of this growth, functional density of thedevices has generally increased by the device feature size or geometryhas decreased. This scaling down process generally provides benefits byincreasing production efficiency, lowering costs, and/or improvingperformance. Such scaling down has also increased the complexities ofprocessing and manufacturing ICs and, for these advances to be realizedsimilar developments in IC fabrication are needed.

Likewise, the demand for increased performance and shrinking geometryfrom ICs has brought the introduction of multi-gate devices. Thesemulti-gate devices include multi-gate fin-type field effect transistors,also referred to as finFET devices, so called because the channel isformed on a “fin” that extends from the substrate. FinFET devices mayallow for shrinking the gate width of device while providing a gate onthe sides and/or top of the fin including the channel region.

As semiconductor devices, such as a metal-oxide-semiconductorfield-effect transistors (MOSFETs), are scaled down through varioustechnology nodes, strained source/drain features (e.g., stressorregions) have been implemented to enhance carrier mobility and improvedevice performance. Stress distorts or strains the semiconductor crystallattice, which affects the band alignment and charge transportproperties of the semiconductor. By controlling the magnitude anddistribution of stress in a finished device, manufacturers can increasecarrier mobility and improve device performance.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIG. 1A is perspective view of an embodiment of a semiconductor devicestructure, in accordance with some embodiments.

FIG. 1B shows a top view of a transistor region, in accordance with someembodiments.

FIG. 2 shows a sequential process flow of forming dislocations in thesource and drain regions of finFET devices, in accordance with someembodiments.

FIGS. 3A-3H show cross-sectional views of the transistor region of thesequential process flow of FIG. 2, in accordance with some embodiments.

FIG. 3I shows a perspective view of the transistor region of FIGS. 3Aand 3B, in accordance with some embodiments.

FIG. 3J shows a perspective view of the transistor region of FIGS. 3Gand 3H, in accordance with some embodiments.

FIG. 4 shows a sequential process flow of forming dislocations in thesource and drain regions of finFET devices, in accordance with someembodiments.

FIGS. 5A-5J show cross-sectional views of the transistor region of thesequential process flow of FIG. 4, in accordance with some embodiments.

FIG. 5K shows a perspective view of the transistor region of FIGS. 5Iand 5J, in accordance with some embodiments.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different features.Specific examples of components and arrangements are described below tosimplify the present disclosure. These are, of course, merely examplesand are not intended to be limiting. Moreover, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed interposing the first and second features, suchthat the first and second features may not be in direct contact. Variousfeatures may be arbitrarily drawn in different scales for simplicity andclarity. Additionally, the present disclosure may repeat referencenumerals and/or letters in the various examples. This repetition is forthe purpose of simplicity and clarity and does not in itself dictate arelationship between the various embodiments. It is understood thatthose skilled in the art will be able to devise various equivalentsthat, although not specifically described herein that embody theprinciples of the present disclosure.

It is also noted that the present disclosure presents embodiments in theform of multi-gate transistors or fin-type multi-gate transistorsreferred to herein as finFET devices. Such a device may include a p-typemetal oxide semiconductor finFET device or an n-typemetal-oxide-semiconductor (NMOS) finFET device. The finFET device may bea dual-gate device, tri-gate device, and/or other configuration. FinFETdevices may be included in an IC such as a microprocessor, memorydevice, and/or other IC. One of ordinary skill may recognize otherembodiments of semiconductor devices that may benefit from aspects ofthe present disclosure.

As described above, strained source/drain features (e.g., stressorregions) have been implemented to enhance carrier mobility and improvedevice performance. Stress distorts or strains the semiconductor crystallattice, which affects the band alignment and charge transportproperties of the semiconductor. By controlling the magnitude anddistribution of stress in a finished device, manufacturers can increasecarrier mobility and improve device performance. Dislocations in thesource and drain regions strain the semiconductor crystalline lattice ofthe transistor regions. As a result, dislocations can be formed toimprove carrier mobility and to improve device performance. The finFETdevices have three-dimensional (3D) gate dielectric layer and usemultiple fins to form source and drain regions. There are uniquechallenges in forming dislocations in the source and drain regions offinFET devices, which do not occur for planar devices.

Illustrated in FIG. 1A is perspective view of a semiconductor devicestructure 100, in accordance with some embodiments. The semiconductordevice structure 100 includes finFET device structures. Thesemiconductor device structure 100 includes a substrate 102, a pluralityof fins 104, a plurality of isolation structures 106, and a gatestructure 108 disposed on each of the fins 104. The gate structure 108may include a gate dielectric layer 115, a gate electrode layer 117,and/or one or more additional layers. A mask layer 120 is over the gateelectrode layer 117. The hard mask layer 120 is used to pattern, such asby etching, the gate structure 108. In some embodiments, the hard masklayer 120 is made of a dielectric material, such as silicon oxide. Theperspective view of FIG. 1A is taken after the patterning (or forming)process of gate structure 108. FIG. 1A shows only one gate structure108. There are additional gate structure(s) (not shown) similar andparallel to the gate structure 108 shown in FIG. 1A. FIG. 1A shows twofins 104. In some embodiments, the number of fins 104 is in a range from2 to 30.

Each of the plurality of fins 104 include a source region 110 _(S) and adrain region 110 _(D), where source or drain features are formed in, on,and/or surrounding the fin 104. A channel region 112 of the fin 104underlies the gate structure 108. The channel region 112 of fin 104 hasa length (gate length) L, and a width (gate width) W, as shown in FIG.1A. In some embodiments, the length (gate length) L is in a range fromabout 10 nm to about 30 nm. In some embodiments, the width (gate width)W is in a range from about 10 nm to about 20 nm. The height (gateheight) H_(G) of gate structure 108, measured from the top of fin 104 tothe top of gate structure 108, is in a range from about 50 nm to about80 nm, in some embodiments. The height (fin height) H_(F) of fin 104,measured from the surface of isolation structure 106 to the top of fin104, is in a range from about 25 nm to about 35 nm, in some embodiments.

The substrate 102 may be a silicon substrate. Alternatively, thesubstrate 102 may comprise another elementary semiconductor, such asgermanium; a compound semiconductor including silicon carbide, galliumarsenic, gallium phosphide, indium phosphide, indium arsenide, and/orindium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs,AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In anembodiment, the substrate 102 is a semiconductor on insulator (SOI).

The isolation structures 106 is made of a dielectric material and may beformed of silicon oxide, silicon nitride, silicon oxynitride,fluoride-doped silicate glass (FSG), a low-k dielectric material, and/orother suitable insulating material. The isolation structures 106 may beshallow trench isolation (STI) features. In an embodiment, the isolationstructures are STI features and are formed by etching trenches in thesubstrate 102. The trenches may then be filled with isolating material,followed by a chemical mechanical polish (CMP). Other fabricationtechniques for the isolation structures 106 and/or the fin structure 104are possible. The isolation structures 106 may include a multi-layerstructure, for example, having one or more liner layers. The level 118of top surfaces and the level 119 of bottom surfaces of isolationstructures 106 are labeled in FIG. 1A.

The fins 104 may provide an active region where one or more devices areformed. In an embodiment, a channel region (112) of a transistor deviceis formed in the fin 104. The fins 104 may comprise silicon or anotherelementary semiconductor, such as germanium; a compound semiconductorincluding silicon carbide, gallium arsenic, gallium phosphide, indiumphosphide, indium arsenide, and/or indium antimonide; an alloysemiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP,and/or GaInAsP; or combinations thereof. The fins 104 may be fabricatedusing suitable processes including photolithography and etch processesin a semiconductor layer 103, which is made of the same material as fins104. Actually, fins 104 are formed by etching the semiconductor layer103. In some embodiments, the semiconductor layer 103 is part ofsubstrate 102. The photolithography process may include forming aphotoresist layer (resist) overlying the substrate (e.g., on a siliconlayer), exposing the resist to a pattern, performing post-exposure bakeprocesses, and developing the resist to form a masking element includingthe resist. The masking element may then be used to protect regions ofthe substrate while an etch process forms a recesses into isolationstructures 106, leaving protruding fins. The recesses may be etchedusing reactive ion etch (RIE) and/or other suitable processes. Numerousother embodiments of methods to form the fins 104 on the substrate 102may be suitable.

The gate structure 108 may include a gate dielectric layer 115, a gateelectrode layer 117, and/or one or more additional layers. In anembodiment, the gate structure 108 is a sacrificial gate structure suchas formed in a replacement gate process used to form a metal gatestructure. In an embodiment, the gate structure 108 includes polysiliconlayer (as the gate electrode layer 117).

The gate dielectric layer 115 of the gate structure 108 may includesilicon dioxide. The silicon oxide may be formed by suitable oxidationand/or deposition methods. Alternatively, the gate dielectric layer ofthe gate structure 108 may include a high-k dielectric layer such ashafnium oxide (HfO₂). Alternatively, the high-k dielectric layer mayoptionally include other high-k dielectrics, such as TiO₂, HfZrO, Ta₂O₃,HfSiO₄, ZrO₂, ZrSiO₂, combinations thereof, or other suitable material.The high-k dielectric layer may be formed by atomic layer deposition(ALD) and/or other suitable methods.

In an embodiment, the gate structure 108 may be a metal gate structure.The metal gate structure may include interfacial layer(s), gatedielectric layer(s), work function layer(s), fill metal layer(s) and/orother suitable materials for a metal gate structure. In otherembodiments, the metal gate structure 108 may further include cappinglayers etch stop layer, and/or other suitable materials. The interfaciallayer may include a dielectric material such as silicon oxide layer(SiO₂) or silicon oxynitride (SiON). The interfacial dielectric layermay be formed by chemical oxidation, thermal oxidation, atomic layerdeposition (ALD), chemical vapor deposition (CVD), and/or other suitableformation process.

Exemplary p-type work function metals that may be included in the gatestructure 108 include TiN, TaN, Ru, Mo, Al, WN, ZrSi₂, MoSi₂, TaSi₂,NiSi₂, WN, other suitable p-type work function materials, orcombinations thereof. Exemplary n-type work function metals that may beincluded in the gate structure 108 include Ti, Ag, TaAl, TaAlC, TiAlN,TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials,or combinations thereof. A work function value is associated with thematerial composition of the work function layer, and thus, the materialof the first work function layer is chosen to tune its work functionvalue so that a desired threshold voltage Vt is achieved in the devicethat is to be formed in the respective region. The work functionlayer(s) may be deposited by CVD, physical vapor deposition (PVD),and/or other suitable process. The fill metal layer may include Al, W,or Cu and/or other suitable materials. The fill metal may be formed byCVD, PVD, plating, and/or other suitable processes. The fill metal maybe deposited over the work function metal layer(s), and thereby fillingin the remaining portion of the trenches or openings formed by theremoval of the dummy gate structure.

The semiconductor device structure 100 described above include fins 104and gate structure 108. The semiconductor device structure 100 needsadditional processing to form various features, such aslightly-doped-drain (LDD) regions and doped source/drain regions, of thetransistor utilizing structure 100. LDD regions are next to channelregions and are under spacers. The term LDD regions are used to describelightly doped regions next to both source and drain regions.

FIG. 1B shows a top view of a transistor region 150 formed with one ofthe fins 104 of FIG. 1A and taken on a surface leveled (118) with thetop surface of isolation structure 106, in accordance with someembodiments. Transistor region 150 includes a source region 110 _(S) anda drain region 110 _(D).

Transistor region 150 also includes a channel region 112, which is partof fin 104 and is surrounded by gate structure 108 on 3 sides, as shownin FIG. 1A. The channel region 112 has a length (gate length) L and awidth (gate width) W. Transistor region 150 also includes gatedielectric layer 115 and gate electrode layer 117. FIG. 1B shows LDDregions between source region 110 _(S) and channel region 112, andbetween drain region 110 _(D) and channel region 112. The LDD regions113 has a width W and a length L_(S), which is defined by the width ofspacers 111. FIG. 1B shows another gate structure 108 by dotted lines.This other gate structure 108 has been described above as being similarand parallel to the gate structure 108 and is not shown in FIG. 1A. Insome embodiments, Ls is in a range from about 5 nm to about 10 nm.

FIG. 2 shows a sequential process flow 200 of forming dislocations inthe source and drain regions of finFET devices, in accordance with someembodiments. FIGS. 3A-3H show cross-sectional views of the transistorregion of the sequential process flow of FIG. 2, in accordance with someembodiments. The processing sequence and structures described below aremainly for n-type finFET devices. However, at least portions of theembodiments described below may be applied for P-type finFET devices.

Process flow 200 begins at an operation 201 during which a substratewith fins and gate structures, such as the one shown in FIG. 1A, isprovided. The substrate undergoes various processing sequences to formthe structures, such as fins 104, isolation structures 106, and gatestructure(s) 108. Spacers (not shown) are then formed at operation 202.The source and drain regions (110 _(D) and 110 _(S)) are recessed andthe dielectric material(s) in isolation structures 106 between thesource and drain regions are removed by etching afterwards at operation203. However, the dielectric material of the isolation structure 106under gate electric layer 117 and spacers 111 is not removed.

Process flow 200 continues to operation 205 in which a pre-amorphousimplantation (PAI) process is performed on the substrate. The processflow 200 then continues to operation 206 in which a stress film isdeposited on the substrate. Afterwards, an anneal process is performedon the substrate at operation 208. Dislocations are formed during theanneal process. As mentioned above, strained source/drain features(e.g., stressor regions) could been implemented to enhance carriermobility and improve device performance. Details of the formation ofdislocations will be described below. The stress film is removed atoperation 210, if applicable. At operation 212, an epitaxial growth isperformed on the substrate to form the source and drain regions. In someembodiment, operations 206 and 208 are not needed and the stress film isnot deposited.

FIGS. 3A-3H are cross-sectional views of intermediate stages of formingsource and drain regions of a finFET structure, in accordance with someembodiments. Spacers 111 are formed at operation 202, as describedabove. Spacers 111 may include a spacer layer (116), which is depositedto provide an offset. As a result, such a spacer layer may also becalled an offset spacer layer 116. In some embodiments, the spacers 111also include another spacer layer, which is called a main spacer layer125. Offset spacer layer 116 has a thickness in a range from about 3 nmto about 10 nm, in some embodiments. Offset spacer layer 116 may be madeof a dielectric material, such as silicon oxynitride (SiON), siliconnitride (SiN), or carbon-doped silicon nitride (SiCN), or carbon dopedsilicon Oxyntride (SiOCN). In some embodiments, an LDD doping isperformed after offset spacer 116 is formed.

Main spacer layer has a thickness in a range from about 5 nm to about 10nm, in some embodiments. Main spacer layer 125 is made of a dielectricmaterial, such as silicon oxynitride (SiON), silicon nitride (SiN), orcarbon-doped silicon nitride (SiCN). SiCN has relative low etch rateagainst etchants, such as H₃PO₄ and HF, in comparison to SiN or SiON. Insome embodiments, the deposition process is a plasma-enhanced chemicalvapor deposition (PECVD) process. Other applicable deposition processmay also be used. In some embodiments, each of spacers 111 has a widthin a range from about 5 nm to about 10 nm.

After spacers 111 are formed, the source and drain regions of n-typedevices are recessed by etching at operation 203. One or more etchingprocesses may be used to recess the source and drain regions. Theetching process(es) may include a dry process(es), such as a plasmaetching process, a wet etching process(es), or a combination of both. Insome embodiments, a wet etch is used to form the recesses. For example,an etchant such as carbon tetrafluoride (CF₄), HF, tetramethylammoniumhydroxide (TMAH), or combinations of thereof, or the like may be used toperform the wet etch and form the recesses. In some embodiments, a layerof SiN of about 50 angstroms thickness may be formed for recessproximity control.

Prior to recessing the source and drain regions of n-type devices, aphotolithography process could be used to cover other regions, such asP-type device regions, on substrate 102, with photoresist to preventetching. As a result, a resist removal process is needed after theetching process and before the next operation. Additional cleaningprocess could be used to ensure no residual resist remains on thesubstrate.

After the source and drain regions of n-type devices are recessed, thedielectric material in the isolation structures 106 neighboring therecessed source and drain regions is removed by etching to expose thesemiconductor layer 103 below and surrounding the isolation structures106. In some embodiment, the etching process is a plasma (dry) etchingprocess. A photoresist patterning process is involved prior to theetching of the dielectric material in the isolation structures 106. Thepatterned photoresist layer protects regions not targeted for theremoval of the dielectric material, such as P-type device regions andSTI structures not neighboring source and drain regions for n-typedevices. By removing isolation dielectric material in the isolationstructures 106 (or removing isolation structures 106), there isadditional areas for subsequent formation of dislocations in the sourceand drain regions, which would be described below. A resist removalprocess is needed after the etching process and before the nextoperation. Additional cleaning process could be used to ensure noresidual resist remains on the substrate.

FIGS. 3A and 3B show cross-sectional views of transistor region 150after recesses 127 are formed and after the dielectric material in theisolation structures 106 is removed and the fins 104 are recessed, inaccordance with some embodiments. The dielectric material in theisolation structures 106 is removed and the fins 104 are recessed inoperation 203 of FIG. 2, as described above. FIG. 3A shows twoneighboring gate structures 108. As mentioned above, there areadditional gate structure(s) similar and parallel to the gate structure108 shown in FIG. 1A. FIG. 3A shows two neighboring gate structures 108are formed over one of the fin 104 and are separated by recesses 127,which are formed by etching source/drain regions 110 _(D) and 110 _(S)of FIG. 1A. For simplicity of discussion, we designate recesses 127 asrecessed drain region (110 _(D)). Each gate structure 108 includes agate electrode layer 117 and a gate dielectric layer 115. A hard masklayer 120 is formed over the gate electrode layer 117, in accordancewith some embodiments. The hard mask layer 120 is used in assistingpatterning of gate structures 108. In some embodiments, the thickness H₁of hard mask layer 120 is in a range from about 70 nm to about 100 nm.The thickness H₂ of gate electrode layer 117 is in a range from about 80nm to about 100 nm. The thickness H₃ of gate dielectric layer 115 is ina range from about 2 nm to about 3 nm. The channel length L as shown inFIG. 1B as equal to the width of gate electrode layer 117 of a gatestructure 108. Channel regions 112, which are directly under the gatestructures 108 are also noted in FIG. 3A. A dotted line 118 indicatesthe level of top surfaces of isolation structures 106 and another dottedline 119 indicates the level of bottom surfaces of isolation structures106.

FIG. 3A also show spacers 111 formed next to the gate structures 108.Each spacer 111 includes an offset spacer layer 116 and a main spacerlayer 125, in accordance with some embodiments. Between neighboring gatestructures 108, there are recesses 127. The depth H_(R) of recesses 127below top surface (level 118) of isolation structures 106 is in a rangefrom about 5 nm to about 20 nm, in some embodiments. The bottom surfaces121 of recesses 127 are marked in FIG. 3A. The bottom surfaced 121 ofrecesses 127 are below the bottom surfaces of isolation structures(marked by level 119).

FIG. 3B shows a cross-sectional view of transistor region 150 accordingto the cut 132 illustrated in FIG. 1A, in accordance with someembodiments. FIG. 3B shows recess 127, which used to be occupied by fins104 (marked as 104 _(O)) and isolation structures 106 (marked as 106_(O)). The boundaries of fins 104 are marked by dotted lines 105. Thedotted line 118 indicating the level of top surfaces of isolationstructures 106 and dotted line 119 indicating the level of bottomsurfaces of isolation structures 106 are also shown in FIG. 3B. Thebottom surface 121 of recesses 127 is marked in FIG. 3A. The bottomsurface 121 of recesses 127 is below the bottom surfaces of isolationstructures (marked by level 119). FIG. 3B shows 2 fins 104 beingremoved. In some embodiments, the number of fins removed is in a rangefrom 2 to 30.

FIG. 3I shows a perspective view of transistor region 150 of FIGS. 3Aand 3B, in accordance with some embodiments. FIG. 3I shows that fins 104have been recessed. In addition, the dielectric material of neighboringisolation structures 106 has been removed and a portion of semiconductorlayer 103 underneath the isolation structures 106 is also removed.Recess 127 includes the regions that used to be occupied by fins 104 andisolation structures 106. In addition, recess 127 also includes aportion of semiconductor layer 103 that has been etched. FIG. 3I alsoshows that portions of isolation structures 106 and fins 104 that arecoved by spacer 111 are not removed and remain over substrate 102,because they are protected by spacer 111 during etching. FIG. 3I shows abottom surface 121 of recess 127.

Referring to FIG. 2, a pre-amorphous implantation (PAI) process isperformed at operation 205 afterwards. The PAI process 230 implants theexposed surface over substrate 102 with some species, as shown in FIGS.3C and 3D in accordance with some embodiments. The implanted speciesdamage the lattice structure of residual fins 104 and semiconductorlayer 103 under openings 106 _(O) to form an amorphized (or amorphous)regions 232. In some embodiments, the implanted species scatter insemiconductor layer 103. The scattered species cause lateralamorphization, which results in amorphized regions 232 extending toregions underneath the spacers 111. In some embodiments, the amorphizedregions 232 are formed in a source and drain region of transistor region150 and do not extend beyond the center line 226 of the gate structure108. The amorphized region 232 has a depth 234 below a top surface 128,which is right next to gate dielectric layer 115, of semiconductor layer103. The amorphized depth 234 is formed according to designspecifications. In some embodiments, the amorphized depth 234 is in arange from about 15 nm to about 60 nm. In some embodiments, theamorphized depth 234 is less than about 100 nm.

FIG. 3D shows that the amorphized region 232 extends below openings 106_(O), which used to be filled with a dielectric material. By removingthe dielectric material of the isolation structures 106, thesemiconductor layer 103 underneath is exposed for amorphization. As aresult, the amorphized region 232 is expanded in comparison to when thedielectric material of the isolation structures 106 is not removed. Theexpanded amorphized region 232 would assist in dislocation formation.Otherwise, the initiation of dislocations would be limited to fins 104.Studies show that dislocations might not form or extend as expected inplanar devices. Details of formation of dislocations which will bedescribed below.

In some embodiments, the amorphized depth 234 is controlled by thethickness of the gate spacers 111, because the gate spacers 111 serve toconcentrate the PAI process 230 implantation energy away from the centerline 226 of the gate structure 108, thereby allowing for a deeperamorphized depth 234. In addition, the amorphized depth 234 iscontrolled by parameters of the PAI process 230, such as implant energy,implant species, and implant dosage, etc. The PAI process 230 implantsthe substrate semiconductor layer 103 with silicon (Si) or germanium(Ge), in accordance with some embodiments. In some embodiments, otherimplant species heavier than Si are used. For example, in someembodiments, the PAI process 230 utilizes other implant species, such asAr, Xe, As, P, In, other suitable implant species, or combinationsthereof. In some embodiments, the PAI process 230 implants species at animplant energy in a range from about 20 KeV to about 40 KeV. In someembodiments, the PAI process 230 implants species at a dosage ranging ina range from about 7×10¹⁴ atoms/cm² to about 1.5×10¹⁵ atoms/cm²,depending on the implantation temperature. Lower implantationtemperature enhances implant amorphization efficiency. In someembodiments, the implant temperature is in a range from about −100° C.to about 25° C. (or room temperature).

In some embodiments, a patterned photoresist layer is utilized to definewhere the amorphized region 232 is formed and protect other regions oversubstrate 102 from implantation damage. For example, the PMOS (p-typeMOS) regions are protected. In addition, the patterned photoresist layerexposes the source/drain regions of n-type metal-oxide-semiconductorfield effect transistor (NMOSFET) regions, such that the source/drainregions are exposed to the PAI process 230 (forming amorphized region232). Alternatively, a patterned hard mask layer, such as a SiN or SiONlayer, is utilized to define the amorphized region. In some embodiments,the patterned photoresist layer or the patterned hard mask layer is partof the current manufacturing process, for example lightly-doped drains(LDD) or source/drain formation, thereby minimizing cost as noadditional photoresist layer or hard mask is required for the PAIprocess 230. After the PAI process is performed, the photoresist oversubstrate 102 is removed.

The process flow 200 then continues to an optional operation 206 inwhich a stress film is deposited on the substrate. Referring to FIGS. 3Eand 3F, an optional stress film 240 is deposited over the substrate 102,in some embodiments. FIG. 3E shows that the stress film 240 is depositedover the gate structures 108 with spacers 111. In some embodiments, thestress film 240 is formed by atomic layer deposition (ALD), chemicalvapor deposition (CVD), physical vapor deposition (PVD), high densityplasma CVD (HDPCVD), other suitable methods, and/or combinationsthereof. In some embodiments, the stress film 240 includes a dielectricmaterial, such as silicon nitride, silicon oxide, silicon oxynitride,other suitable materials, and/or combinations thereof. The stress film240 has tensile stress, which affects the recrystallization process. Forexample, the stress film 240 could retard the growth rate in the [110]crystalline direction of the source and drain regions. In someembodiments, the stress film 240 is not used. In some embodiments, thethickness of the stress film 240 is in a range from about 5 nm to about20 nm. In some embodiments, the stress of film 240 is in a range fromabout 0.8 GPa to about 2.0 GPa. In some embodiments, the stress film 240is tensile and provides compressive stress to the S/D regions.

Afterwards, an anneal process is performed on the substrate at operation208. Still referring to FIGS. 3E and 3F, an annealing process 250 isperformed on the substrate 102 at operation 208. The annealing process250 causes the amorphized regions 232 to re-crystallize, formingstressor regions 252. This process is often referred to as solid-phaseepitaxy regrowth (SPER), and thus, the stressor regions 252 are referredto as epi regions. The stressor regions 252 include epitaxial SiP,epitaxial SiC, epitaxial SiCP or epitaxial Si, or a combination thereof,in accordance with some embodiments. SiC stands for carbon-containingsilicon and SiCP stands for carbon-and-phosphorous-containing silicon.In some embodiments, the carbon concentration is less than about 3atomic %. In some embodiments, the P concentration is in a range fromabout 5E19 1/cm³ to about 5E21 1/cm³. The dopants of the stressorregions are doped in the layer(s) during deposition (or doped in-situ).In some embodiments, stressor regions 252 include epitaxial layers withdifferent dopants. In some embodiments, the epitaxial layers include aSiP layer with the P concentration is in a range from about 1E20 1/cm³to about 7E20 1/cm³ with a thickness in a range from about 4 nm to about10 nm over another SiP layer the P concentration is in a range fromabout 1E21 1/cm³ to about 3E2 1/cm³. In some embodiments, the epitaxiallayers include a SiCP layer with a thickness in a range from about 4 nmto about 10 nm and the C concentration less than about 1% and the Pconcentration is in a range from about 1E20 1/cm³ to about 7E20 1/cm³over another a SiP layer the P concentration is in a range from about1E21 1/cm³ to about 3E2 1/cm³. In some embodiments, the surface layer ofthe stress regions 252 is a Si layer to prevent the loss of P duringsubsequent processing.

In some embodiments, carbon is doped into a silicon film to create a SiCstressor, which is compressive and applies a tensile strain to then-type metal-oxide-semiconductor (NMOS) transistor channel region due tothe small size of carbon (C) in comparison to silicon (Si). In addition,in some embodiments, the compressive film stress in the stressor regionsassists the initiation of pinchoff. In some embodiments, P is doped tolower the resistance of the source and drain regions. Carbon could beadded to impede the out-diffusion of P.

In some embodiments, the annealing process 250 is a microwave annealing(MWA) process, a rapid thermal annealing (RTA) process, a millisecondthermal annealing (MSA) process (for example, a millisecond laserthermal annealing process), or a micro-second thermal annealing (μSA)process. In some embodiments, the annealing process includes a pre-heatoperation which minimizes or even eliminates end of range (EOR) defects,which are the remained defects at the amorphous/crystalline interface.The pre-heat operation is performed at a temperature from about 200° C.to about 700° C., in accordance with some embodiments. The pre-heatoperation is performed in a range from about 10 seconds to about 10minutes, in some embodiments.

For advanced device manufacturing that prohibits high temperatureprocessing at this process operation, a MWA process may be used for themain anneal. MWA process can be tuned to locally increase temperature ofa particular structure, layer, or region, such as amorphized regions232, to a much higher value than the substrate or other surroundingstructures, layers, or regions. For example, the amorphized regions 232have dopants and crystalline structures that are different from thesurrounding semiconductor layer 103 and substrate 102. As a result, theamorphized region 232 could be heated up to a higher temperature thansemiconductor layer 103 and substrate 102 by microwave. The local highertemperature may be caused by electronic polarization and/or interfacialpolarization mechanism under microwave. The local temperature of thetargeted layer is higher than the substrate. In some embodiments, thetemperature difference is in a range from about 200° C. to about 500° C.As a result, the temperature (measured on the substrate) of the MWA canbe set at a lower value. In some embodiments, the MWA process is in arange from about 400° C. to about 600° C. In some embodiments, thesubstrate temperature is in a range from about 300° C. to about 500° C.during the 1^(st) period with the electronic polarization mechanism. Insome embodiments, the substrate temperature is in a range from about500° C. to about 600° C. during the 2^(nd) period with the interfacialpolarization mechanism. The duration of the MWA process is in a rangefrom about 1 min to about 3 minutes, in some embodiments. If MWA processis used, the temperature of the pre-heat operation is maintained to bein a range that meets the requirement of the manufacturing process.

Alternatively, there are other types of annealing processes. In someembodiments, the main anneal of the annealing process 250 is performedat a temperature in a range from about 800° C. to about 1,400° C.Depending on the type of annealing process and the temperature utilized,the main anneal of the annealing process 250 is performed for a durationin a range from about 1 millisecond to about 5 hours, in someembodiments. For example, the pre-heat operation is at a temperature ofabout 550° C. for about 180 seconds. If the annealing process 250 is aRTA process, in some embodiments, the main anneal temperature is equalto or greater than about 950° C. and is performed for a duration in arange from about 0.5 second to about 5 seconds, in some embodiments. Ifthe annealing process 250 is a MSA process, in some embodiments, themain anneal temperature is up to a Si melting point of about 1,400° C.and is performed for a few milliseconds or less, for example for about0.8 milliseconds to about 100 milliseconds.

During the annealing process 250, as the stressor regions 252recrystallize, dislocations 260 are formed in the stressor regions 252.As described above, FIG. 3B shows a cross-sectional view of transistorregion 150 according to the cut 132 illustrated in FIG. 1A. FIG. 3Fshows a cross-sectional view derived from FIG. 3B. The exposed surfaceof semiconductor layer 103 of FIG. 3F (parallel to cut 132 or parallelto cut 131) has a [100] crystalline orientation and the crystallineorientation of semiconductor layer 103 p perpendicular to cut 132 is[110], as shown in FIG. 3F in accordance with some embodiments. Asdescribed above in FIG. 3D, the semiconductor layer 103 underneath isexposed for amorphization, by removing the dielectric material of theisolation structures 106. As a result, the amorphized regions 232 areexpanded in comparison to when the dielectric material of the isolationstructures 106 is not removed. During the anneal process 250, theexpanded amorphized regions 232 increase the sizes of the regions forstarting dislocations (or pinchoff points 262). In some embodiments, thedislocations 260 are formed in the [111] direction. In some embodiments,the [111] direction has an angle θ in a range from about 45 to about 65degrees, with the angle being measured with respect to [110], which isparallel to the top surface 128 of the semiconductor layer 103 (orsurface of substrate 102), as shown in FIGS. 3E and 3F. The exposedsurface of semiconductor layer 103 of FIG. 3E (parallel to cut 131) hasa crystalline orientation of [110]. Pinchoff points 262 are below thebottom surfaces 121 of recesses 127.

The dislocations 260 start formation at pinchoff points 262. In someembodiments, the pinchoff points 262 are formed in the stressor regions252 at depths H_(D) in a range from about 10 nm to about 30 nm, with thedepths H_(D) being measured from the bottom surface 119 of isolationstructure 106. The pinchoff points 262 have a horizontal buffer 264 anda vertical buffer 266. The horizontal buffer 264 and the vertical buffer266 are measured from the boundaries of amorphized regions 232 and aremarked by dotted lines in FIGS. 3C, 3D, 3E and 3F. The horizontal buffer264 and the vertical buffer 266 are formed according to designspecifications and are affected by the annealing process 250. Thepinchoff points 262 have a horizontal buffer 264 in a range from about 8nm to about 38 nm and a vertical buffer 266 in a range from about 10 nmto about 40 nm, in some embodiments. In some embodiments, the pinchoffpoints 262 are formed such that the pinchoff points 262 are not disposedwithin the channel region. FIG. 3F shows the cross-sectional view ofdislocations 260, which are represented by dots and are below bottomsurface 121.

After the annealing process 250, the stress film 240 is removed atoperation 210, as described above for FIG. 2. In some embodiments, atleast a portion of each gate spacer 111 of NMOS devices is also removed.The stress film 240 and the removed portions of gate spacers 111 areremoved by an etching process. In some embodiments, the etching processis performed by wet etching, such as by using phosphoric acid orhydrofluoric acid, or by a combination of dry etching and wet etching.In some embodiments, the process sequence of performing PAI process,formation of stress film, annealing, and removal of stress filmdescribed above are repeated a number of times to create multipledislocations. Further details of multiple dislocations in the stressregions 252 are found in U.S. patent application Ser. No. 13/177,309,entitled “A Semiconductor Device with a Dislocation Structure and Methodof Forming the Same” and filed on Jul. 6, 2011, which is incorporatedherein by reference in its entirety.

Afterwards, a silicon-containing epitaxial structure 285 is formed ineach of the recesses 127, as shown in FIGS. 3G and 3H, at operation 212of FIG. 2 to form source and drain regions, in accordance with someembodiments. The silicon-containing epitaxial structures 285 are used asthe source and drain structures for devices in transistor region 150.The silicon-containing structure 285 is formed by performing anepitaxial deposition process to form a silicon-containing epitaxialmaterial, in some embodiments. In some embodiments, thesilicon-containing epitaxial material (stress-inducing material)includes SiC, SiCP, SiP or other material that produces tensile strainon the transistor channel region. In some embodiments, thesilicon-containing material is formed by using a silicon-containingprecursor. For example, in some embodiments, gases, such as silane(SiH₄), disilane (S_(i2)H₆), trisilane (S_(i3)H₈), dichlorosilane(SiH₂Cl₂), etc., are used to form SiC-containing epitaxial material instructure 285. In some embodiments, phosphorous-containing gas, such asphosphine (PH₃), is used to form SiP epitaxial material or to form SiCPwith a carbon-containing gas. In other embodiments forming P-typetransistors, the silicon-containing epitaxial material includes anymaterial, such as SiGe, that produces compressive strain on thetransistor channel region.

In some embodiments, the surfaces 286 of the silicon-containingepitaxial structure 285 are concave and are at about the same level withor higher the surface 128 of semiconductor layer 103 and the gatestructure 108. Surfaces 286 are concave due to difference in growth ratebetween [100] and [111] crystalline orientations. In some embodiments,the surface 286 has a height of up to about 30 nm above the substratesurface 223. Since the silicon-containing epitaxial structures 285 arealso epitaxial, the dislocations 260 continue in structures 285, asshown in FIG. 3G, in accordance with some embodiments. With the growthof dislocations 260, epitaxial structures 285 become part of stressorregions 252, which are source and drain regions.

FIG. 3J shows a perspective view of transistor region 150 of FIGS. 3Gand 3H, in accordance with some embodiments. FIG. 3J shows that thesilicon-containing epitaxial structure 285 is formed in recess 127 ofFIG. 3I. Portions of epitaxial structure 285 protrude over theneighboring semiconductor layer 103. The bottom surface 121 of recess127 is also noted in FIG. 3J. FIG. 3J also shows the cross-sectionalview of dislocations 262, which are represented by dots and are belowbottom surface 121.

In some embodiments, the silicon-containing epitaxial material is formedby chemical vapor deposition (CVD), e.g., low pressure CVD (LPCVD),atomic layer CVD (ALCVD), ultrahigh vacuum CVD (UHVCVD), reducedpressure CVD (RPCVD), any suitable CVD, molecular beam epitaxy (MBE)process, any suitable epitaxial process; or any combinations thereof. Insome embodiments, the deposition of the silicon-containing epitaxialmaterial has a deposition temperature of about 750° C. or less. In otherembodiments, the etching temperature ranges from about 500° C. to about750° C. In some embodiments, the pressure of the deposition processranges from about 50 Torr to about 600 Torr.

Alternatively, the silicon-containing epitaxial material is formed byperforming a cyclic deposition and etch process to form asilicon-containing epitaxial material. Details of an exemplary processare described in U.S. patent application Ser. No. 13/029,378, entitled“Integrated Circuits and Fabrication Methods Thereof” and filed on Feb.17, 2011. The above-mentioned application is incorporated herein byreference in their entirety.

Afterwards, substrate 102 undergoes further CMOS or MOS technologyprocessing to form various features to complete forming the devicestructures and interconnect in device region 150. In an embodiment, thegate stack contains polysilicon in the final device. In anotherembodiment, a gate replacement process (or gate last process) isperformed, where the gate electrode 117 is replaced with a metal gate.The metal gate includes liner layers, work function layers, conductivelayers, metal gate layers, fill layers, other suitable layers, and/orcombinations thereof. The various layers include any suitable material,such as aluminum, copper, tungsten, titanium, tantalum, tantalumaluminum, tantalum aluminum nitride, titanium nitride, tantalum nitride,nickel silicide, cobalt silicide, silver, TaC, TaSiN, TaCN, TiAl, TiAlN,WN, metal alloys, other suitable materials, and/or combinations thereof.

In some embodiments, subsequent processing further forms variouscontacts/vias/lines and multilayer interconnect features (e.g., metallayers and interlayer dielectrics) over substrate 102, configured toconnect the various features or structures. In some embodiments, theadditional features provide electrical interconnection to the device.For example, a multilayer interconnection includes verticalinterconnects, such as conventional vias or contacts, and horizontalinterconnects, such as metal lines. In some embodiments, the variousinterconnection features implement various conductive materialsincluding copper, tungsten, and/or silicide. In one example, a damasceneand/or dual damascene process is used to form a copper relatedmultilayer interconnection structure.

The mechanism for forming dislocations in the source and drain regionsdescribed above in FIG. 3A-3H enables consistent and reliable formationof dislocations to exert tensile stress in the channel regions.

The process flow 200 of FIG. 2 performs PAI (operation 205) prior toepitaxial grown (operation 212). Alternatively, dislocations in thesource and drain regions may be formed by different flows. FIG. 4 showsa sequential process flow 400 of forming dislocations in the source anddrain regions of finFET devices, in accordance with some embodiments.FIGS. 5A-5J show cross-sectional views of the transistor region of thesequential process flow of FIG. 2, in accordance with some embodiments.The processing sequence and structures described below are mainly forn-type finFET devices. However, at least portions of the embodimentsdescribed below may be applied for P-type finFET devices.

Process flow 400 begins at an operation 401 during which a substratewith fins and gate structures, such as the one shown in FIG. 1A, isprovided. Operation 401 is similar to operation 201 and structuresprovided in operation 401 are similar to those of operation 201. Spacers(not shown) are then formed at operation 402. The source and drainregions (110 _(D) and 110 _(S)) are recessed and the isolationstructures 106 between the source and drain regions are then removed toexpose semiconductor layer 103 by etching at operation 403. Operations402 and 403 are similar to operations 202 and 203, respectively.

Process flow 400 continues to operation 405 in which an epitaxial growthis performed on the substrate to form the source and drain regions. Theprocess flow then continues to operation 406 in which a pre-amorphousimplantation (PAI) process is performed on the substrate. The processflow 200 then continues to an operation 407 in which a stress film isdeposited on the substrate. Afterwards, an anneal process is performedon the substrate at operation 408. The stress film is removed atoperation 410. Process flow 400 performs the epitaxial growth of thesource and drain regions prior to performing the PAI process. As aresult, the dislocations formed would be closer to the surface (128) ofthe semiconductor layer 103 than process flow 200. The locations ofpinchoff points, such as 262, affect the tensile stress applied on tothe fin channels.

FIGS. 5A-5J are cross-sectional views of intermediate stages of formingsource and drain regions of a finFET structure, in accordance with someembodiments. Since operations 401, 402, and 403 are similar tooperations 201, 202, and 203 respectively, FIGS. 5A-5B are similar toFIGS. 3A-3B respectively, the description for FIGS. 5A-5B can bereferred to description for FIGS. 3A-3B.

Referring to FIG. 4, an epitaxial growth is performed on the substrateto form the source and drain regions at operation 405 after operation404 is completed. The epitaxial growth forms silicon-containingepitaxial structures 285*, which are used as the source and drainstructures for devices in transistor region 150*. The silicon-containingstructures 285* are formed by performing an epitaxial deposition processto form a silicon-containing epitaxial material, in some embodiments.The silicon-containing epitaxial material of the silicon-containingstructures 285* is similar to the material of silicon-containingepitaxial structures 285 described above in FIGS. 3G and 3H. However,dislocations in the epitaxial structures 285* designed to stress thesource and drain regions have not been formed yet.

In some embodiments, the surface 286* of the silicon-containingepitaxial structure 285* is level with or higher than the surface 128 ofsemiconductor layer 103 and the gate structure 108. In some embodiments,the surface 286* has a height of up to about 30 nm above surface 108.

Referring to FIG. 4, a pre-amorphous implantation (PAI) process isperformed at operation 406 after operation 405 is completed. The PAIprocess 230* implants the exposed surface over substrate 102 with somespecies, as shown in FIGS. 5E and 5F in accordance with someembodiments. The implanted species damage the lattice structure of thesilicon-containing structures 285* and portions of semiconductor layer103 neighboring the silicon-containing structures 285*. In someembodiments, the implanted species scatter in semiconductor layer 103.The scattered species cause lateral amorphization, which results inamorphized region 232* (with boundaries in dotted lines near theboundaries of structures 285*) extending to regions underneath thespacers 111. The amorphized regions 232* are formed in a source anddrain regions in transistor region 150* and does not extend beyond thecenter line 226 of the gate structure 108. The amorphized region 232*has a depth 234* below the top surface 118 of the original isolationstructure 106. The depth 234* is formed according to designspecifications. In some embodiments, the distance 234* is in a rangefrom about 30 nm to about 50 nm. In some embodiments, the amorphizeddepth 234* is less than about 60 nm. PAI process 230* and implant dosagerange are similar to PAI process 230 described above, in someembodiments. The bottom surface of amorphized region 232* is marked by adotted line 123 in FIG. 5F, in accordance with some embodiments.

The process flow 400 then continues to an optional operation 407 inwhich a stress film is deposited on the substrate. Referring to FIGS. 5Gand 5H, a stress film 240* is deposited over the substrate 102, in someembodiments. FIG. 5G shows that the stress film 240* is deposited overthe gate structures 108 with spacers 111. Stress film 240* is similar tostress film 240 described above.

Afterwards, an anneal process is performed on the substrate at operation408. Referring to FIGS. 5G and 5H, an annealing process 250* isperformed on the substrate 102 at operation 408. The annealing process250* causes the amorphized regions 232* to re-crystallize, formingstressor regions 252*. This process is often referred to as solid-phaseepitaxial regrowth (SPER), and thus, the stressor regions 252* arereferred to as epi regions. The annealing process 250* is similar toannealing process 250 described above. The stressor regions 252* areamorphized regions 232* after they are re-crystallized and thedislocations are formed. Since PAI process 230* is performed after thesilicon-containing epitaxial structures 285* are formed, the depths 234*of stressor regions 252* (or amorphized regions 232*) are lower thandepth 234 of stressor regions 252 (or amorphized regions 232) of FIGS.5E and 5G.

As described above, the semiconductor layer 103 underneath is exposedfor amorphization, by removing the dielectric material of the isolationstructures 106. Similar to amorphized regions 232, the amorphizedregions 232* are expanded in comparison to when the dielectric materialof the isolation structures 106 are not removed. During the annealprocess 250*, the expanded amorphized regions 232* increase the sizes ofregions for starting dislocations 262*. In some embodiments, thedislocations 260* are formed in the [111] direction. In someembodiments, the [111] direction has an angle θ* in a range from about45 to about 65 degrees, with the angle being measured with respect to[110], as shown in FIG. 5G.

The dislocations 260* start formation at pinchoff points 262*. In someembodiments, the pinchoff points 262* are formed in the stressor regions252* at depths H_(D)*in a range from about 5 nm to about 20 nm, thedepths H_(D)* being measured from the bottom surface 119 of isolationstructure 106. Since PAI process 230* is performed after thesilicon-containing epitaxial structures 285* are formed, the depths 234*of stressor regions 252* (or amorphized regions 232*) are lower thandepth 234 of stressor regions 252 (or amorphized regions 232) of FIGS.5E and 5G. As a result, the depths H_(D)* of dislocations 260* are lowerthan the depths H_(D) of dislocations 260 described above.

FIG. 5K shows a perspective view of transistor region 150* of FIGS. 5Iand 5J, in accordance with some embodiments. FIG. 5K shows that thesilicon-containing epitaxial structure 285* is formed in recess 127 ofFIG. 3I, which is also a perspective view of FIGS. 5A and 5B. Portionsof epitaxial structure 285* protrude over the neighboring semiconductorlayer 103. The bottom surface 121 of recess 127 is also noted in FIG.5K. FIG. 5K also shows the cross-sectional view of dislocations 262*,which are represented by dots and are above bottom surface 121.

The pinchoff points 262* have a horizontal buffer 264* and a verticalbuffer 266*. The horizontal buffer 264* and the vertical buffer 266* areformed according to design specifications and are affected by theannealing process 250*. The pinchoff points 262* have a horizontalbuffer 264* in a range from about 8 nm to about 38 nm and a verticalbuffer 266* in a range from about 10 nm to about 40 nm, in someembodiments. In some embodiments, the pinchoff points 262* are formedsuch that the pinchoff points 262* are not disposed within the channelregion.

After the annealing process 250*, the stress film 240* is removed atoperation 410, as described above for FIG. 4 and as shown in FIGS. 5Iand 5J, in accordance with some embodiments. In some embodiments, atleast a portion of each gate spacer 111 of NMOS devices is also removed.The stress film 240* and the removed portions of gate spacers 111 areremoved by an etching process. In some embodiments, the etching processis performed by wet etching, such as by using phosphoric acid orhydrofluoric acid, or by dry etching using suitable etchant. In someembodiments, the process sequence of performing PAI process, formationof stress film, annealing, and removal of stress film described aboveare repeated a number of times to create multiple dislocations. Furtherdetails of multiple dislocations in the stress regions 252 are found inU.S. patent application Ser. No. 13/177,309, entitled “A SemiconductorDevice with a Dislocation Structure and Method of Forming the Same” andfiled on Jul. 6, 2011, which is incorporated herein by reference in itsentirety.

Afterwards, substrate 102 undergoes further CMOS or MOS technologyprocessing to form various features to complete forming the devicestructures and interconnect of device region 150* in a manner similar todevice region 150. The mechanism for forming dislocations in the sourceand drain regions described above in FIGS. 5A-5J also enables consistentand reliable formation of dislocations to exert tensile stress in thechannel regions.

Dislocations 260 or 260* described above strain source/drain regions (orforming stressor regions). They are formed in the source and regions toenhance carrier mobility and improve device performance. The finFETdevices have three-dimensional (3D) gate dielectric layer and usemultiple fins to form source and drain regions. The fins have limitedcrystalline regions for forming dislocation. By removing the dielectricmaterial in the isolation structures 106 surrounding fins 104, thecrystalline regions for forming dislocations are increased. As a result,dislocations in the stressor regions (or source and drain regions) canform consistently to produce targeted strain in the source and drainregions to improve carrier mobility and device performance for NMOS.

The embodiments of mechanisms for forming dislocations in the source anddrain regions described above in FIGS. 3A-3H and FIGS. 5A-5J both enableconsistent and reliable formation of dislocations to exert tensilestress in the channel regions. The consistent and reliable formation ofdislocations is achieved by recessing fins and by removing the isolationstructures between fins to increase the regions to form dislocations.Without removing the isolation structures between fins, the regionsallowed for forming dislocations are limited to the fin regions, whichare more limited and could limit the generation of dislocations. Byusing the mechanisms described above, the NMOS finFET devices couldimprove on current (Ion) in a range from about 5% to about 20% in someembodiments.

Embodiments of mechanisms for forming dislocations in source and drainregions of finFET devices are provided. The mechanisms involve recessingfins and removing the dielectric material in the isolation structuresneighboring fins to increase epitaxial regions for dislocationformation. The mechanisms also involve performing a pre-amorphousimplantation (PAI) process either before or after the epitaxial growthin the recessed source and drain regions. An anneal process after thePAI process enables consistent growth of the dislocations in the sourceand drain regions. The dislocations in the source and drain regions (orstressor regions) can form consistently to produce targeted strain inthe source and drain regions to improve carrier mobility and deviceperformance for NMOS devices.

In some embodiments, a semiconductor device is provided. Thesemiconductor device includes a substrate having a fin-typefield-effect-transistor (finFET) region. The semiconductor device alsoincludes two neighboring gate structures formed over two neighboring finstructures, and the two neighboring fin structures contain a crystallinesilicon-containing material. Portions of the two neighboring finstructures protrude above neighboring isolation structures. Thesemiconductor device further includes source and drain regions for bothof the two neighboring gate structures, and there are dislocations inthe source and drain regions to strain the source and drain regions.

In some other embodiments, a semiconductor device is provided. Thesemiconductor device includes a substrate having a fin-typefield-effect-transistor (finFET) region, and two neighboring gatestructures formed over two neighboring fin structures. The twoneighboring fin structures contain a crystalline silicon-containingmaterial, and portions of the two neighboring fin structures protrudeabove neighboring isolation structures. The semiconductor device alsoincludes source and drain regions for both of the two neighboring gatestructures, and there are dislocations in the source and drain regionsto strain the source and drain regions. The source and drain regionsextends to neighbor the isolation structures between the two neighboringgate structures, and there is no isolation structures in the source anddrain regions.

In yet some other embodiments, a method of forming a fin-typefield-effect-transistor (finFET) device is provided. The method includesproviding a substrate with a plurality of fins and a plurality of gatestructures, and the plurality of gate structures are formed over theplurality of fins. There are isolation structures formed between theplurality of fins. The method also includes recessing exposed portionsthe plurality of fins and removing a dielectric material of theisolation structures, and performing a pre-amorphous implantation (PAI)process on portions of a semiconductor layer to amorphize the portionsof the semiconductor layer. The method further includes performing ananneal process to recrystallize amorphized portions of the semiconductorlayer, and growing an epitaxial silicon-containing material on therecrystallized portions of the semiconductor layer to form source anddrain regions of the finFET device.

In yet another embodiment, a method of forming a fin-typefield-effect-transistor (finFET) device is provided. The method includesproviding a substrate with a plurality of fins and a gate structure,wherein the gate structure is formed over the plurality of fins, andwherein isolation structures are over the substrate between adjacentones of the plurality of fins, and recessing exposed portions theplurality of fins and removing a dielectric material of the isolationstructures between the plurality of fins to form exposed portions of thesubstrate. A pre-amorphous implantation (PAI) process is performed onportions of the exposed portions of the substrate to form amorphizedportions, and an anneal process is performed to recrystallize theamorphized portions. The method includes growing an epitaxialsilicon-containing material on the recrystallized portions to formsource and drain regions of the finFET device.

In yet another embodiment, a method of forming a fin-typefield-effect-transistor (finFET) device is provided. The method includesforming a first fin and a second fin extending from a substrate, anisolation structure being on the substrate between the first fin and thesecond fin, the first fin and the second fin protruding through theisolation structure, forming a gate structure over the first fin, thesecond fin, and the isolation structure, and recessing the first fin andthe second fin on opposing sides of the gate structure. The methodfurther includes removing the isolation structure between the first finand the second fin along opposing sides of the gate structure, theremoving exposing at least a portion of the substrate under theisolation structure, and forming an epitaxial region over remainingportions of the first fin, remaining portions of the second fin, and theportion of the substrate exposed by the removing.

In yet another embodiment, a method of forming a fin-typefield-effect-transistor (finFET) device is provided. The method includesforming a first fin extending from a substrate and an isolationstructure on opposing sides of the first fin, the first fin extendingabove the isolation structure, and forming a gate structure over thefirst fin, the gate structure extending over a portion of the isolationstructure. The method further includes recessing the first fin onopposing sides of the gate structure, thereby exposing a first portionof the substrate, removing the isolation structure on opposing sides ofthe gate structure, thereby exposing a second portion of the substrate,amorphizing at least a portion of the first portion and the secondportion of the substrate, thereby forming an amorphized region of thesubstrate. A semiconductor material is epitaxially grown over the firstportion and the second portion of the substrate, and the amorphizedregion of the substrate recrystallized, thereby forming a recrystallizedregion.

It is understood that different embodiments disclosed herein offerdifferent disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure. For example, the embodimentsdisclosed herein describe formation of a tensile stress in a fin region.However, other embodiments may include forming a compressive stress infin region by providing the relevant stress layer (e.g.,stress-transferring layer) overlying the fin region. Examples ofcompressive stress generating films may include metal nitridecompositions.

What is claimed is:
 1. A method of forming a fin-typefield-effect-transistor (finFET) device, the method comprising:providing a substrate with a plurality of fins and a gate structure,wherein the gate structure is formed over the plurality of fins, andwherein isolation structures are over the substrate between adjacentones of the plurality of fins; recessing exposed portions of theplurality of fins and removing a dielectric material of the isolationstructures between the plurality of fins to form exposed portions of thesubstrate, wherein an upper surface of the exposed portions of thesubstrate is lower than an upper surface of the substrate betweenadjacent fins below the gate structure; performing a pre-amorphousimplantation (PAI) process on portions of the exposed portions of thesubstrate to form amorphized portions; performing an anneal process torecrystallize the amorphized portions; and growing an epitaxialsilicon-containing material on the recrystallized portions to formsource and drain regions of the finFET device.
 2. The method of claim 1,wherein the PAI process is performed before the growing of the epitaxialsilicon-containing material.
 3. The method of claim 1, furthercomprising: depositing a stress film before the anneal process; andremoving the stress film after the anneal process.
 4. The method ofclaim 1, wherein the epitaxial silicon-containing material is astress-inducing material, wherein the stress-inducing material includesSiC, SiP, or SiCP.
 5. The method of claim 1, wherein the anneal processis a microwave anneal (MWA) process.
 6. The method of claim 5, whereinsubstrate temperature of the MWA is in a range from about 400° C. toabout 600° C.
 7. A method of forming a fin-type field-effect-transistor(finFET) device, the method comprising: forming a first fin and a secondfin extending from a substrate, an isolation structure being on thesubstrate between the first fin and the second fin, the first fin andthe second fin protruding through the isolation structure; forming agate structure over the first fin, the second fin, and the isolationstructure; removing the isolation structure between the first fin andthe second fin along opposing sides of the gate structure, the removingexposing at least an exposed portion of the substrate under theisolation structure; recessing the first fin, the second fin, and theexposed portion of the substrate, wherein an upper surface of theexposed portions of the substrate is lower than an upper surface of thesubstrate between adjacent fins below the gate structure; forming anamorphized region; and forming an epitaxial region over remainingportions of the first fin, remaining portions of the second fin, and theportion of the substrate exposed by the removing.
 8. The method of claim7, further comprising, prior to forming the epitaxial region, forming anamorphized region by performing a pre-amorphization implant into theremaining portions of the first fin, remaining portions of the secondfin, and the portion of the substrate exposed by the removing.
 9. Themethod of claim 8, further comprising recrystallizing the amorphizedregion.
 10. The method of claim 9, wherein after recrystallizing,dislocations have pinchoff points at depths in a range from about 5 nmto about 30 nm below a bottom surface of the gate structure.
 11. Amethod of forming a fin-type field-effect-transistor (finFET) device,the method comprising: forming a first fin and a second fin extendingfrom a substrate and an isolation structure interposed between the firstfin and the second fin, the first fin and the second fin extending abovethe isolation structure; forming a gate structure over the first fin andthe second fin, the gate structure extending over a portion of theisolation structure; recessing the first fin and the second fin onopposing sides of the gate structure, thereby exposing a first portionof the substrate; removing the isolation structure on opposing sides ofthe gate structure, thereby exposing a second portion of the substrate,wherein an upper surface of the exposed portions of the substrate islower than an upper surface of the substrate between adjacent fins belowthe gate structure; amorphizing at least a portion of the first portionand the second portion of the substrate, thereby forming an amorphizedregion of the substrate; epitaxially growing a semiconductor materialover the first portion and the second portion of the substrate; andrecrystallizing the amorphized region of the substrate, thereby forminga merged source/drain, wherein dislocations are in the mergedsource/drain.
 12. The method of claim 11, wherein the amorphizing isperformed prior to the epitaxially growing the semiconductor material.13. The method of claim 11, further comprising forming a stress filmover the semiconductor material.
 14. The method of claim 13, wherein theforming the stress film is performed prior to recrystallizing.
 15. Themethod of claim 11, wherein after recrystallizing, dislocations in therecrystallized region have pinchoff points at depths in a range fromabout 5 nm to about 30 nm below a bottom surface of the gate structure.